1. Field of the Invention
The present invention relates to a system for detecting a fault block in a semiconductor device such as a CMOS device formed by a plurality of logic blocks.
2. Description of the Related Art
In a prior art system for testing a semiconductor device, the device is driven using a functional test pattern, and as a result, an output pattern is obtained at the outputs of the device. Then, the output pattern is compared with an expected pattern. Thus, a determination of whether the device is normal or abnormal is made based on whether the output pattern coincides with the expected pattern.
After it is determined that the device is abnormal, a fault point is estimated in accordance with a fault dictionary for storing a relationship between functional test patterns and output patterns for virtual faults.
The fault dictionary is made by carrying out fault simulation.
In the above-described prior art testing apparatus, however, when the device is highly-integrated, a large number of fault simulations are required to complete the fault dictionary.
In addition, the volume of the fault dictionary is very large. For example, EQU V.sub.0 .varies.L.sup.2.about.3
where V.sub.0 is the volume of the fault dictionary; and
L is a number of logic circuits in the device.
Thus, it is extremely difficult to determine a fault point of a highly-integrated semiconductor device.